Presently, most memory systems are either constructed from static random access memory devices (SRAMs) or dynamic random access memory devices (DRAMs). Each type of memory device has advantages and disadvantages, and as a result DRAMs and SRAMS are typically restricted to different applications. SRAMs are faster and are typically used in applications where fast access times and high bandwidth are critical, such as in cache memories. SRAMs however consume more power, are more expensive to fabricate, and provide fewer cells (bits) per given chip space. On the other hand, while slower than SRAMs, DRAMs are typically less expensive, consume substantially less power, and provide more bits in the same chip space. DRAMs are typically used to construct larger memory subsystems, such as system memories and display frame buffers, and in other instances where high speed is not critical.
One particular reason DRAMs have a speed disadvantage compared to SRAMs is a result of the fact that most DRAMs are constructed from dynamic circuitry. Dynamic memory circuitry operates in dynamic cycles each of which consists of two different subcycles, namely an active cycle (subcycle) and a precharge cycle (subcycle) (this is in contrast to fully static SRAMs which do not require a precharge cycle). During the active cycle, which are typically 60-70 nanoseconds in length, addresses are presented and accesses to corresponding locations performed. During the intervening precharge cycle, also approximately 60-70 nanoseconds in length, the dynamic circuitry prepares for the next active cycle. Generally, critical nodes are brought to their optimum voltages, with some circuitry, such as the row and column decoder circuitry brought to ground, while other circuitry, such as the sense amplifiers are brought to equilibrium (i.e. the bitlines are equalized to a predetermined voltage). Additionally, the wordlines are all (typically) brought to ground. While the dynamic circuitry of DRAMs conserves power since unused circuitry is turned-off during precharge, the two cycle operation results in a latency penalty vis-a-vis fully static SRAMs which operate only in an active cycle.
By eliminating or minimizing the latency penalty which DRAMs suffer, substantial improvements is speeds could be achieved. In view of the fact that DRAMs are less expensive, consume less power, and provide more storage cells per chip than SRAMs, such an improvement would be highly advantageous. With improved speed, DRAMs can be used in higher bandwidth applications, including some of those which presently require the use of SRAMs. Thus, the need has arisen for improved dynamic random access memories, improved methods of operating dynamic random access memories, and systems using the same.